1. Field of the Invention
The present invention relates to an insulated gate field effect transistor having an LDD (Lightly Doped Drain) structure and further having a high breakdown voltage and a method of making the same.
2. Description of the Related Art
In an insulated gate field effect transistor (IGFET), an inverted region called a channel is provided between source and drain regions at a surface portion of a semiconductor substrate which contacts a gate insulating film, and the channel is used as a current path between the source and drain regions. With a fine device structure, the channel length of the IGFET is greatly reduced. As the channel length is decreased, various influences such as a decrease in threshold voltage (Vth), a leakage current generated by a punch-through phenomenon in a sub-threshold region, and variations in characteristics caused by hot carriers occur. In order to eliminate the above disadvantages, an LDD structure has been adopted. According to the LDD structure, a lightly doped region is provided so as to contact heavily doped source and drain regions or a heavily doped drain region.
With the above structure, a peak field strength of a drain depletion layer formed under a pinch-off condition can be relieved. The punch-through phenomenon is a phenomenon in which a current flows through the semiconductor substrate when the depletion layer of the drain region is brought into contact with the depletion layer of the source region, and the punch-through phenomenon increases a leakage current. More specifically, the phenomenon is not preferable for transistors such as transfer transistors in DRAMs or CMOS inverters which are easily affected by the leakage current. In order to prevent the punch-through phenomenon, it is effective that an impurity is ion-implanted into the semiconductor substrate such that a peak concentration position is located near the deepest portion of the source/drain regions in the depth direction of the semiconductor substrate. That is, a channel stop (deep channel region) is provided below the channel region by an impurity.
FIG. 10A is a sectional view showing an N-channel IGFET having a conventional LDD structure.
A P-type semiconductor substrate having an impurity concentration of, e.g., about 1.times.10.sup.15 cm.sup.-3 is used as a semiconductor substrate 10, and a gate insulating film 2 is provided on the major surface of the semiconductor substrate 10. The gate insulating film, i.e., a gate oxide film, is formed by thermal oxidation or CVD techniques, and is constituted by a silicon oxide film (SiO.sub.2) having a thickness of about 1,000 to 2,000.ANG.. A gate electrode 1 of polysilicon or the like having a thickness of about 4,000.ANG. and a gate length L of about 5 .mu.m is formed over the gate insulating film 2. N-type source/drain regions 3 and 4 are formed in the semiconductor substrate 10 below the gate electrode 1. The source region 3 is provided by a low concentration impurity region (to be referred to as a lightly doped region hereinafter) 31 and a high concentration impurity diffusion region (to be referred to as a heavily doped region hereinafter) 32, and the drain region 4 is also constituted by a lightly doped region 41 and a heavily doped region 42, thereby providing an LDD structure. The lightly doped regions 31 and 41 are opposed to each other through a channel region (shallow channel region), and partially extends below the gate electrode 1. Although the heavily doped regions 32 and 42 are formed in the lightly doped regions 31 and 41, respectively, the heavily doped regions 32 and 42 from the substrate surface are deeper than the lightly doped regions 31 and 41.
A channel region 5 is provided in the semiconductor substrate 10 below the gate electrode 1 located between the lightly doped regions 31 and 41, and an effective channel length L.sub.eff of the channel region 5 is about 3 .mu.m. In order to improve the punch-through resisting property, a channel stop 6 is provided below the channel region 5. An impurity concentration profile of the channel stop 6 in the depth direction (XB--XB sectional) of the semiconductor substrate 10 is shown in FIG. 10B. The peak impurity concentration of the channel stop 6 is about 1.times.10.sup.16 cm.sup.-3. An impurity concentration profile of the channel stop 6 in the horizontal direction of the semiconductor substrate 10 is almost constant, but an impurity concentration profile of the channel stop 6 in the depth direction of the semiconductor substrate 10 has the peak concentration (about 1.times.10.sup.16 cm.sup.-3) at an almost central portion of the width in the depth direction. The depth position (about 0.4 .mu.m) having the peak concentration is almost equal to that of the deepest portion of the lightly doped regions 31 and 41 in the source/drain regions. The depth of each of the lightly doped regions 31 and 41 is about 0.35 .mu.m, and the peak concentration is about 1.times.10.sup.17 cm.sup.-3. Since the depth of the peak impurity concentration of the channel stop 6 is almost equal to each of that of the bottom of each of the lightly doped regions 31 and 41, the channel stop 6 partially overlaps the lightly doped regions 31 and 41.
The channel region and channel stop of the IGFET are generally formed by ion-implantation techniques. A deep ion-implantation for preventing the punch-through is accomplished to provide the channel stop, while a shallow ion-implantation for controlling a threshold value is carried out to form the channel region. These ion-implantation processes are performed to an element forming region surrounded by an isolation region formed in the semiconductor substrate, and then source/drain regions are provided. However, as in the present invention, when the IGFET having a high breakdown voltage of more than 20 V is required, a difference between the concentration of the lightly doped region of the source/drain regions and the peak impurity concentration of the channel stop is relatively low. Therefore, when the channel stop overlaps the source/drain regions, a predetermined concentration cannot be obtained. Therefore, the channel stop is prevented from overlapping the source/drain regions by using a mask such as a photoresist. However, the channel stop inevitably overlaps the lightly doped source/drain regions.
This is because an alignment margin is determined in consideration of a mask alignment error. In addition, a PN junction of the drain region is shallowly formed in each overlapped portion. For this reason, a field relief effect of the LDD structure can not be obtained, thereby lowering the breakdown voltage and the reliability. Further, in the case of reducing the gate length L, when the effective channel length L.sub.eff defined by the gate length is reduced to less than about 3 .mu.m, the breakdown voltage is decreased as indicated by a characteristic curve B in FIG. 2, and the punch-through occurs. Therefore, an IGFET having the effective channel length smaller than about 3 .mu.m cannot be practically used to limit the fine device structure. Although the curve B in FIG. 2 is obtained by using the IGFET having the breakdown voltage of 40 V. However, even if the breakdown voltage is higher or lower than 40 V, the effective channel length of the IGFET having high reliability is limited to about 3 .mu.m as described above. That is, when the breakdown voltage is in the range of 20 to 80 V, the conventional IGFET has the same characteristic as indicated by the characteristic curve B in FIG. 2.
The breakdown voltage shown in FIG. 2 is almost proportional to the thickness of the gate oxide film. That is, an IGFET having the breakdown voltage of 20 V has a gate oxide film having a thickness of about 500.ANG., and an IGFET having the breakdown voltage of 80 V has a gate oxide film having a thickness of about 2,000.ANG.. The gate oxide film of the IGFET having the breakdown voltage of 40 V shown in FIG. 2 has a thickness of about 1,150.ANG.. In the case of forming the lightly doped region in the source region, when the channel stop overlaps the source region in the depth direction, the width of the lightly doped source region is decreased. For this reason, the source resistance is increased to decrease a current driving force.